题解 | #不重叠序列检测#

序列检测一般有两种办法，一种是利用移位寄存器来实现，这种方法比较简单。另一种是利用状态机来实现，难点在于状态转移图的绘制。下面使用状态机来实现。

对于不重叠检测，具体思路就是未发生错误时正常跳转到下一个s状态。如果发生错误，普通序列检测状态机是跳转至之前的某个s状态，对于本题，我的想法是跳转到某个计数状态sw，例如在检测第一位数就发生错误时，下一个状态就是sw5,计数等待5个时钟，然后返回初始状态s0。再例如例如在检测第二位数发生错误时，下一个状态就是sw4,计数等待4个时钟，然后返回初始状态s0，以此类推。

对于输出match和not_match，因为题目中并未延迟一个周期，所以我采用assign赋值。判断依据就是，当next_state == S0时，curr_state是否处于s6或者sw状态。

首先画出状态转移图

然后根据状态转移图，写出三段式状态机，代码如下。

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output match,
	output not_match
	);
    parameter    S0 = 4'd0,
                S1 = 4'd1,
                S2 = 4'd2,
                S3 = 4'd3,
                S4 = 4'd4,
                S5 = 4'd5,
                S6 = 4'd6,
                SW5 = 4'd7,
                SW4 = 4'd8,
                SW3 = 4'd9,
                SW2 = 4'd10,
                SW1 = 4'd11,
                SW0 = 4'd12;
                
     
    reg [3:0] curr_state,next_state,cnt;
    //状态跳转
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 0)
            curr_state <= S0;
        else
            curr_state <= next_state;
    end
    //状态转移逻辑
    always@(*)begin
        case(curr_state)
            S0:next_state = data ? SW5 : S1 ;
            S1:next_state = data ? S2 : SW4 ;
            S2:next_state = data ? S3 : SW3 ;
            S3:next_state = data ? S4 : SW2 ;
            S4:next_state = data ? SW1 : S5 ;
            S5:next_state = data ? SW0 : S6 ;
            S6:next_state = S0 ;
            SW5:next_state = (cnt == 4) ? S0 : SW5;
            SW4:next_state = (cnt == 3) ? S0 : SW4;
            SW3:next_state = (cnt == 2) ? S0 : SW3;
            SW2:next_state = (cnt == 1) ? S0 : SW2;
            SW1:next_state = (cnt == 0) ? S0 : SW1;
            SW0:next_state = S0;
            default:next_state = S0;
        endcase
    end
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 0)
            cnt <= 0;
        else if(curr_state != next_state)
            cnt <= 0;
        else
            cnt <= cnt + 1;
    end
    //输出，使用时序将match延后一个周期，不延后可以用assign  match = (curr_state == S8);
    //注意，使用assign需将match类型改为wire。
    /*always@(posedge clk or negedge rst_n) begin
        if(rst_n == 0)
            match <= 0;
        else
            match = (curr_state == S6)&&(next_state == S0);
    end*/
    assign match = (curr_state == S6)&&(next_state == S0);
    /*always@(posedge clk or negedge rst_n) begin
        if(rst_n == 0)
            not_match <= 0;
        else
            not_match = (next_state == S0)&&((curr_state == SW6)||(curr_state == SW5)||(curr_state == SW4)||(curr_state == SW3)||(curr_state == SW2)||(curr_state == SW1));
    end*/
    assign not_match = (next_state == S0)&&((curr_state == SW5)||(curr_state == SW4)||(curr_state == SW3)||(curr_state == SW2)||(curr_state == SW1)||(curr_state == SW0));
endmodule