题解 | #整数倍数据位宽转换8to16#

````timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
    localparam IDLE = 0,
                S1 = 1,
                S2 = 2,
                S3 = 3,
                S4 = 4,
                S5 = 5;
    reg[2:0]curr_state,next_state;
    
    always @(posedge clk or negedge rst)begin
        if(~rst)begin
           curr_state <= IDLE; 
        end else
            curr_state <= next_state;
    end
    
    always @(*)begin
        case(curr_state)
            IDLE: next_state = (data==1'b1)? S1: IDLE;
            S1  : next_state = (data==1'b0)? S2: S1;
            S2  : next_state = (data==1'b1)? S3: IDLE;
            S3  : next_state = (data==1'b1)? S4: IDLE;
            S4  : next_state = (data==1'b1)? S5: IDLE;
            S5  : next_state = (data==1'b1)? S1: IDLE;
            default: next_state = IDLE;
        endcase
    end
    
    always @(posedge clk or negedge rst)begin
        if(~rst)
            flag <= 1'b0;
        else if(next_state==S5)
            flag <= 1'b1;
        else
            flag <= 1'b0;
    end

//*************code***********//
endmodule