题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
    input clk,
    input rst_n,
    input data,
    input data_valid,
    output reg match
    );
    reg [3:0] data_reg;
    always @(posedge clk or negedge rst_n) begin
        if(~rst_n)  data_reg <= 'b0;
        else begin
            if(data_valid) data_reg <= {data_reg[2:0],data};
            else data_reg <= data_reg;
        end 
    end

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            match <= 0;
        end 
        else if((data_reg==4'b0011)&&data_valid&&(data==0)) match<=1;
        else match <=0;
    end
  
endmodule