题解 | #并串转换#

直接左移好像也可以通过啊？data <= data << 1;//左移

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);
    

//*************code***********//
    reg [3:0] data = 4'd0;
    reg [1:0] cnt;
    reg valid;
    
    assign dout = data[3];
    assign valid_in = valid;
    
    always @ (posedge clk, negedge rst) begin
        if(!rst) begin
            data <= 4'b0;
            cnt <= 2'b0;
            valid <= 1'b0;
        end
        else begin
            if  (cnt == 2'b11) begin
                data <= d;
                cnt <= 2'b0;
                valid <= 1'b1;
            end
            else begin
                cnt <= cnt + 1'b1;
                valid <= 1'b0;
                //data <= {data[2:0], data[3]};//循环左移
                data <= data << 1;//直接左移
            end
        end
    end
        
    


//*************code***********//

endmodule

循环左移

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);
    

//*************code***********//
    reg [3:0] data = 4'd0;
    reg [1:0] cnt;
    reg valid;
    
    assign dout = data[3];
    assign valid_in = valid;
    
    always @ (posedge clk, negedge rst) begin
        if(!rst) begin
            data <= 4'b0;
            cnt <= 2'b0;
            valid <= 1'b0;
        end
        else begin
            if  (cnt == 2'b11) begin
                data <= d;
                cnt <= 2'b0;
                valid <= 1'b1;
            end
            else begin
                cnt <= cnt + 1'b1;
                valid <= 1'b0;
                data <= {data[2:0], data[3]};//循环左移
                //data <= data << 1;//循环左移
            end
        end
    end
        
    


//*************code***********//

endmodule