题解 | #数据串转并电路#

````timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
  localparam IDLE=0, S1=1, S10=2, S101=3, S1011=4, S10111=5;
    reg [2:0] state, n_state;
    always@(posedge clk or negedge rst )
        if(!rst) state <= IDLE;
    else state <= n_state;
    always@(*)
        case(state)
            IDLE:n_state = data? S1:IDLE;
            S1:  n_state = data? S1:S10;
            S10: n_state = data? S101:IDLE;
            S101:n_state = data? S1011:S1;
            S1011:n_state = data? S10111:S10;
            S10111:n_state = IDLE;
            default:n_state = IDLE;
        endcase
    always@(posedge clk or negedge rst)begin
        if(!rst) flag <= 1'b0;
    else if(n_state == S10111) flag <= 1'b1;
        else flag <= 1'b0;
    end
//*************code***********//
endmodule
没说明是同步复位还是异步复位吧