题解 | #含有无关项的序列检测#

timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
    reg [3:0]val;
    always@(posedge clk or negedge rst_n)
        if(!rst_n) val <= 4'b0;
        else if(data_valid) val <= {val[2:0], data};
        else val <= 4'b0;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) match <= 0;
        else if({val[2:0], data} == 4'b0110) match <= 1;
        else match <= 0;
    end
endmodule