题解 | #含有无关项的序列检测#

````timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
    //first way
   reg [9:0] state;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)  state <= 9'b0;
        else state <= {state[7:0], a};
    end
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) match <= 0;
        else 
           /* casez(state)
             9'b011zzz110: match <= 1;
             default: match <= 0;
        endcase*/
            if(state[8:6]==3'b011 && state[2:0]==3'b110) match <= 1;
            else match <= 0;
    end
    //second way
    /*localparam IDLE=0, S0=1, S01=2, S011=3, B1=4, B2=5, B3=6, SB1=7, SB11=8, SB110=9;
    reg [3:0] state, next_state;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) state <= IDLE;
        else state <= next_state;
    end
    always@(*)begin
        case(state)
            IDLE:next_state = a? IDLE:S0;
            S0:  next_state = a? S01:S0;
            S01: next_state = a? S011:S0;
            S011:next_state = B1;
            B1:  next_state = B2;
            B2:  next_state = B3;
            B3:  next_state = a? SB1:S0;
            SB1: next_state = a? SB11:S0;
            SB11:next_state = a? IDLE:SB110;
            SB110:next_state = a? S01:S0;
        endcase
    end
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) match <= 0;
        else if(state == SB110) match <= 1;
        else match <= 0;
    end*/
endmodule