题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
    reg [3:0] num;
    always@(posedge clk or negedge rst_n) begin: count
        if(~rst_n) begin
            num <= 4'b0;
        end
        else if(~set) begin
            num <= num + 1;
        end
        else begin
            num <= set_num;
        end
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            number <= 0;
        else
            number <= num;
    end
    
    always@(posedge clk or negedge rst_n) begin: gen_zero
        if(~rst_n)
            zero <= 0;
        else if(num == 4'd0)
            zero <= 1;
        else
            zero <= 0;
    end
endmodule