题解 | #输入序列连续的序列检测#
输入序列不连续的序列检测
http://www.nowcoder.com/practice/f96d0e94ec604592b502b0f1800ed8aa
1.移位寄存器+上升沿检测电路（寄存器保持目标结果可能是好几个周期）
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
input data_valid,
output match
);
//parameter
parameter N = 4;
//defination
reg [N - 1 : 0] SR;
wire match_0;
reg match_r;
//output
always@(posedge clk or negedge rst_n)begin
if(!rst_n) SR <= 'd0;
else if(data_valid) SR <= {SR[2 : 0], data};
end
assign match_0 = (SR == 4'b0110);
always@(posedge clk or negedge rst_n)begin
if(!rst_n) match_r <= 'd0;
else match_r <= match_0;
end
assign match = match_0 && !match_r;
endmodule
2.借鉴别的同学代码，突然发现这么写更简单
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input data,
input data_valid,
output reg match
);
//parameter
parameter N = 4;
//defination
reg [N - 1 : 0] SR;
//output
always@(posedge clk or negedge rst_n)begin
if(!rst_n) SR <= 'd0;
else if(data_valid) SR <= {SR[2 : 0], data};
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n) match <= 'd0;
else if(data_valid && SR[2 : 0] == 3'b011 && !data) match <= 1'b1;
else match <= 1'b0;
end
endmodule