`timescale 1ns/1ns module triffic_light ( input rst_n, //异位复位信号,低电平有效 input clk, //时钟信号 input pass_request, output wire[7:0]clock, output reg red, output reg yellow, output reg green ); reg [7:0]cnt; wire add_cnt; wire end_cnt; reg [1:0]state,next; wire R2Y,Y2G,G2R,I2R; parameter RED = 2'b00,YEL = 2...