`timescale 1ns/1ns module top_module( input [15:0] in, output [15:0] out ); genvar i ; generate for (i=0 ;i <= 15 ; i = i + 1) begin: loop //这里一定要打标签 assign out[i] = in[15-i]; end endgenerate /*assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7],in[8],in[9],in[10],in[11],in[12], in[13],...