①请用Verilog实现此优先编码器
`timescale 1ns/1ns module encoder_0( input [8:0] I_n , output reg [3:0] Y_n ); //直接用case //casez,casex,case都可以综合,case进行全等匹配,casez忽略?或z对应的位进行匹配,casex忽略x、?或z对应的位进行匹配。 always@(*)begin casex(I_n) 9'b1_1111_1111:Y_n=4'b1111; 9'b0_xxxx_xxxx:Y_n=4'b0110; 9'b1_0xxx_xxxx:Y_n=4'b0111; 9'b1_10xx_xxxx:Y_n=4'b1000; 9'b1_110x_xxxx:Y_n=4'b1001; 9'b1_1110_xxxx:Y_n=4'b1010; 9'b1_1111_0xxx:Y_n=4'b1011; 9'b1_1111_10xx:Y_n=4'b1100; 9'b1_1111_110x:Y_n=4'b1101; 9'b1_1111_1110:Y_n=4'b1110; default:Y_n=0; endcase end endmodule
`timescale 1ns/1ns module encoder_0( input [8:0] I_n, output reg [3:0] Y_n ); integer i; reg loop_break; //a flag to do the loop break like in C++ always @(*) begin Y_n = 4'b1111; loop_break = 0; for (i = 0; i <= 8 && !loop_break; i = i + 1) begin if (!I_n[8 - i]) begin Y_n = 4'b0110 + i; loop_break = 1; // set the flag to true to break the loop end end end endmodule
`timescale 1ns/1ns module encoder_0( input [8:0] I_n , output reg [3:0] Y_n ); always@(*)begin casex(I_n) 9'b1111_1111_1: Y_n = 4'b1111; 9'b0xxx_xxxx_x: Y_n = 4'b0110; 9'b10xx_xxxx_x: Y_n = 4'b0111; 9'b110x_xxxx_x: Y_n = 4'b1000; 9'b1110_xxxx_x: Y_n = 4'b1001; 9'b1111_0xxx_x: Y_n = 4'b1010; 9'b1111_10xx_x: Y_n = 4'b1011; 9'b1111_110x_x: Y_n = 4'b1100; 9'b1111_1110_x: Y_n = 4'b1101; 9'b1111_1111_0: Y_n = 4'b1110; default:Y_n = 4'b0000; endcase end endmodule完全没有取反
我的想法是x状态在真值表上代表的并不是不定态,而是无关项。另外,我的解法受到上一题的影响,所以选择用复杂的门级描述完成。
另外,输入、输出都是低电平有效的,所以我是把输出真值表的高电平部分作为编写表达式的起点的,所以不需要再对表达式取反。
`timescale 1ns/1ns module encoder_0( input [8:0] I_n , output [3:0] Y_n ); assign Y_n[0] = ( I_n[0]&I_n[1]&I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[7]&I_n[8] | ~I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[1]&I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8]); assign Y_n[1] = ( I_n[0]&I_n[1]&I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[8] | ~I_n[7]&I_n[8] | ~I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[0]&I_n[1]&I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8]); assign Y_n[2] = ( I_n[0]&I_n[1]&I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[8] | ~I_n[7]&I_n[8] | ~I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[1]&I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[0]&I_n[1]&I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] ); assign Y_n[3] = ( I_n[0]&I_n[1]&I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[6]&I_n[7]&I_n[8] | ~I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[1]&I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8] | ~I_n[0]&I_n[1]&I_n[2]&I_n[3]&I_n[4]&I_n[5]&I_n[6]&I_n[7]&I_n[8]); endmodule
希望能够对你有所帮助。
module encoder_0( input wire [8:0] I_n, output reg [3:0] Y_n ); always@(*)begin if(I_n[8]==1'b0) Y_n=4'b0110; else if(I_n[7]==1'b0) Y_n=4'b0111; else if(I_n[6]==1'b0) Y_n=4'b1000; else if(I_n[5]==1'b0) Y_n=4'b1001; else if(I_n[4]==1'b0) Y_n=4'b1010; else if(I_n[3]==1'b0) Y_n=4'b1011; else if(I_n[2]==1'b0) Y_n=4'b1100; else if(I_n[1]==1'b0) Y_n=4'b1101; else if(I_n[0]==1'b0) Y_n=4'b1110; else Y_n=4'b1111; end endmodule
always @* begin case(left_one) 9'b0_0000_0001 : Y_n = 4'd6; 9'b0_0000_0010 : Y_n = 4'd7; 9'b0_0000_0100 : Y_n = 4'd8; 9'b0_0000_1000 : Y_n = 4'd9; 9'b0_0001_0000 : Y_n = 4'd10; 9'b0_0010_0000 : Y_n = 4'd11; 9'b0_0100_0000 : Y_n = 4'd12; 9'b0_1000_0000 : Y_n = 4'd13; 9'b1_0000_0000 : Y_n = 4'd14; 9'b0_0000_0000 : Y_n = 4'd15; default : Y_n = 4'd6; endcase end
`timescale 1ns/1ns module encoder_0( input [8:0] I_n , output reg [3:0] Y_n ); always @ (*) begin if (~I_n[8]) Y_n = 4'b0110; else if (~I_n[7]) Y_n = 4'b0111; else if (~I_n[6]) Y_n = 4'b1000; else if (~I_n[5]) Y_n = 4'b1001; else if (~I_n[4]) Y_n = 4'b1010; else if (~I_n[3]) Y_n = 4'b1011; else if (~I_n[2]) Y_n = 4'b1100; else if (~I_n[1]) Y_n = 4'b1101; else if (~I_n[0]) Y_n = 4'b1110; else Y_n = 4'b1111; end endmodule