题解 | 不重叠序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

reg [2:0]cnt;
always@(posedge clk or negedge rst_n) begin
	if (~rst_n)
	cnt <= 'd0;
	else
	if (cnt == 'd5)
	cnt <= 'd0;
	else
	cnt <= cnt + 'd1;
end

parameter S0 = 3'd0;
parameter S1 = 3'd1;
parameter S2 = 3'd2;
parameter S3 = 3'd3;
parameter S4 = 3'd4;
parameter S5 = 3'd5;
parameter fail = 3'd6;

reg [2:0]cur_state, nxt_state;

always@(posedge clk or negedge rst_n) begin
	if (!rst_n)
	cur_state <= S0;
	else
	cur_state <= nxt_state;
end

always@(*) begin
	case(cur_state)
	S0:	nxt_state = data ? fail : S1;
	S1:	nxt_state = data ? S2 : fail;
	S2:	nxt_state = data ? S3 : fail;
	S3:	nxt_state = data ? S4 : fail;
	S4:	nxt_state = data ? fail : S5;
	S5:	nxt_state =  S0;
	fail:	nxt_state = (cnt=='d5) ? S0 : fail;
	
	default : nxt_state = fail;
	endcase
end

always@(posedge clk or negedge rst_n) begin
	if (~rst_n) begin
		match <= 1'b0;
		not_match <= 1'b0;
	end
	else
	if (cnt == 'd5) begin
		if (cur_state==S5 && ~data) begin
			match <= 1'b1;
			not_match <= 1'b0;
		end
		else begin
			match <= 1'b0;
			not_match <= 1'b1;
		end
	end
	else begin
		match <= 1'b0;
		not_match <= 1'b0;
	end
end
	
endmodule