题解 | 数据串转并电路

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

//串并转换电路
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		ready_a <= 1'b0;
	end
	else begin
		ready_a <= 1'b1;
	end
end

reg [2:0] cnt_bit;	//比特计数器
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cnt_bit <= 'd0;
	end
	else if(cnt_bit == 'd5) begin
		cnt_bit <= 'd0;
	end
	else if(valid_a)begin
		cnt_bit <= cnt_bit + 1;
	end
end

reg [5:0] data;		//数据拼接
always@(*)begin
	if(!rst_n)begin
		data <= 'd0;
	end
	else if(valid_a) begin
		data[cnt_bit]<=data_a;
	end
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		valid_b <= 1'b0;
	end
	else if(cnt_bit == 'd5) begin
		valid_b <= 1'b1;
	end
	else begin
		valid_b <= 1'b0;
	end
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		data_b <= 'd0;
	end
	else if(cnt_bit == 'd5) begin
		data_b <= data;
	end
end

endmodule