题解 | 任意奇数倍时钟分频

`timescale 1ns/1ns

module clk_divider
    #(parameter dividor = 5)
( 	input clk_in,
	input rst_n,
	output clk_out
);
parameter WIDTH = $clog2(dividor-1);
reg[WIDTH:0] cnt;

reg clk_f;
reg clk_r;

always@(posedge clk_in or negedge rst_n)begin
	if(!rst_n) begin
		cnt <= 'd0;
	end
	else if(cnt == dividor-1)begin
		cnt <= 'd0;
	end
	else begin
		cnt <= cnt + 1'b1;
	end
end

always@(posedge clk_in or negedge rst_n)begin
	if(!rst_n)begin
		clk_r <= 1'b0;
	end
	else if(cnt == (dividor-1)>>1)begin
		clk_r <= 1'b1; 
	end
	else if(cnt == dividor-1) begin
		clk_r <= 1'b0;
	end
end

always@(negedge clk_in or negedge rst_n)begin
	if(!rst_n)begin
		clk_f <= 1'b0;
	end
	else if(cnt == (dividor-1)>>1) begin
		clk_f <= 1'b1;
	end
	else if(cnt == dividor-1) begin
		clk_f <= 1'b0;
	end
end

assign clk_out = clk_f | clk_r;

    
endmodule