题解 | 位拆分与运算

module data_cal(
    input   [15:0]  d,//输入数据
    input   [1:0]   sel,//输入位选信号
    input           clk,
    input           rst,
    output reg [4:0]out,//数据相加结果
    output reg      validout
    );
reg [15:0]  d1;
always @(posedge clk or negedge rst) begin
    if (!rst)
        out <= 'b0;
    else
        case(sel) 
            'd0: begin
                out <= 'b0;
                d1  <= d;   //sel为0时输入的值有效
            end
            'd1: begin
                out <= d1[3:0] + d1[7:4];
            end
            'd2: begin
                out <= d1[3:0] + d1[11:8];
            end
            'd3: begin
                out <= d1[3:0] + d1[15:12];
            end
            default:
                out <= out;
        endcase
end

always @(posedge clk or negedge rst) begin
    if (!rst)
        validout <= 'b0;
    else
        validout <= ~(sel == 'b0); 
end
endmodule