题解 | 状态机与时钟分频

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
    localparam [1:0] S0 = 2'b00;
    localparam [1:0] S1 = 2'b01;
    localparam [1:0] S2 = 2'b10;
    localparam [1:0] S3 = 2'b11;
    reg [1:0] cs, ns;
    always @(posedge clk or negedge rst) begin
        if (!rst) begin
            cs <= S0;
        end else begin
            cs <= ns;
        end
    end
    always @(*) begin
        if (!rst) begin
            ns = S0;
            clk_out = 0;
        end else begin
            case (cs)
                S0: begin
                    ns = S1;
                    clk_out = 0;
                end
                S1: begin
                    ns = S2;
                    clk_out = 1;
                end
                S2: begin
                    ns = S3;
                    clk_out = 0;
                end
                S3: begin
                    ns = S0;
                    clk_out = 0;
                end
            endcase
        end
    end

//*************code***********//
endmodule

注意波形图实在S1状态是发生的时钟电平拉高