题解 | 任意小数分频

`timescale 1ns / 1ns

module div_M_N (
    input  wire clk_in,
    input  wire rst,
    output wire clk_out
);
    parameter M_N = 8'd87;
    parameter c89 = 8'd24;  // 8/9时钟切换点
    parameter div_e = 5'd8;  //偶数周期
    parameter div_o = 5'd9;  //奇数周期
    //*************code***********//
    reg [7:0] cnt;
    reg [4:0] cnt_e, cnt_o;
    always @(posedge clk_in or negedge rst) begin
        if (!rst) begin
            cnt   <= 0;
            cnt_e <= 0;
            cnt_o <= 0;
        end else if (cnt == M_N - 1) begin
            cnt <= 0;
        end else begin
            if (cnt < c89) begin
                cnt_o <= 0;
                if (cnt_e == div_e - 1) begin
                    cnt_e <= 0;
                end else begin
                    cnt_e <= cnt_e + 1;
                end
            end else begin
                cnt_e <= 0;
                if (cnt_o == div_o - 1) begin
                    cnt_o <= 0;
                end else begin
                    cnt_o <= cnt_o + 1;
                end
            end
            cnt <= cnt + 1;
        end
    end
    reg clk_out_reg;
    always @(posedge clk_in or negedge rst) begin
        if (!rst) begin
            clk_out_reg <= 0;
        end else if (cnt < c89) begin
            if (cnt_e == 'd0 || cnt_e == div_e >> 1) begin
                clk_out_reg <= ~clk_out_reg;
            end
        end else if (cnt >= c89) begin
            if (cnt_o == 'd0 || cnt_o == (div_o - 1) >> 1) begin
                clk_out_reg <= ~clk_out_reg;
            end
        end
    end
    assign clk_out = clk_out_reg;
    //*************code***********//
endmodule

注意在always块中，每个条件分支需要把所有被控信号的赋值完全覆盖例如cnt_e和cnt_o的交互