题解 | 根据状态转移写状态机-二段式

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
//状态转移图--->输出仅有当前状态决定-->Moore
reg [2:0] current_state,next_state;
always@(posedge clk or negedge rst)
if(!rst)
  current_state <= 3'd0;
else
  current_state <= next_state;

always@(*)
  case(current_state)
  3'd0:begin
	next_state = data ? 3'd1:3'd0;
	flag = 0;
  end
  3'd0:begin
	next_state = data ? 3'd1:3'd0;
	flag = 0;
  end
  3'd1:begin
	next_state = data ? 3'd2:3'd1;
	flag = 0;
  end
  3'd2:begin
	next_state = data ? 3'd3:3'd2;
	flag = 0;
  end
  3'd3:begin
	next_state = data ? 3'd4:3'd3;
	flag = 0;
  end
  3'd4:begin
	next_state = data ? 3'd1:3'd0;
	flag = 1;
  end
  default: next_state = 3'd0;
  endcase


//*************code***********//
endmodule