题解 | 移位运算与乘法

`timescale 1ns / 1ns
module  multi_sel(
    input [7:0] d,
    input clk,
    input rst,
    output reg input_grant,
    output reg [10:0] out
);
    reg [1:0] mul_case = 0;
    reg [7:0] d_reg = 0;


    always @(posedge clk or negedge rst) begin
        if (!rst) begin
            out <= 0;
            d_reg<=d;
            input_grant <= 0;
        end else begin
            case (mul_case)
                2'b00: begin
                    d_reg<=d;
                    input_grant <= 1;
                    out<=d;
                end
                2'b01: begin
                    out <= (d_reg << 1) + d_reg;
                    input_grant <= 0;
                    
                end
                2'b10: begin
                    out <= (d_reg << 3) - d_reg;
                    input_grant <= 0;
                    
                end
                2'b11: begin
                    out <= (d_reg << 3);
                    input_grant <= 0;
                    
                end
            endcase

        end
    end

    always @(posedge clk or negedge rst)begin
        if(!rst) begin
            mul_case<=2'b00;
        end else begin
            mul_case<=mul_case+2'b1;
        end
    end

endmodule  //shift_mul

状态机要单独写在另一个always块中，不然会扰乱时序！！！