题解 | 占空比50%的奇数分频

解法一、

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg [2:0] cnt_pos,cnt_neg;
reg flag1;
reg flag2;
reg clk_out;

always@(posedge clk_in or negedge rst)
    if (~rst)
        cnt_pos <= 'd0;
    else if(cnt_pos == 'd3)
        cnt_pos <= 'd0;
    else if(~flag1)
        cnt_pos <= cnt_pos + 1'b1;

always@(negedge clk_in or negedge rst)
    if (~rst)
        cnt_neg <= 'd0;
    else if(cnt_neg == 'd3)
        cnt_neg <= 'd0;
    else if(flag2)
        cnt_neg <= cnt_neg + 1'b1;

always@(posedge clk_in or negedge rst)
    if (~rst)
        flag1 <= 'd0;
    else if(cnt_pos == 'd3 || cnt_neg == 'd3)
        flag1 <= ~flag1; 

always@(negedge clk_in or negedge rst)
    if (~rst)
        flag2 <= 'd0;
    else if(cnt_pos == 'd3 || cnt_neg == 'd3)
        flag2 <= ~flag2;

always @(*)           
    begin                                        
        if(!rst)                               
             clk_out = 1'b0;                                   
        else if(~clk_out)                                
             clk_out = flag2? ~clk_out : clk_out;                                    
        else if(clk_out)                                
             clk_out = ~flag1? ~clk_out : clk_out;                                    
    end 

assign clk_out7 = clk_out;
//*************code***********//
endmodule

解法二、

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg [2:0] cnt;
reg flag1;
reg flag2;
reg clk_out;

always@(posedge clk_in or negedge rst)
    if (~rst)
        cnt <= 'd0;
    else if(cnt == 'd6)
        cnt <= 'd0;
    else
        cnt <= cnt + 1'b1;

always@(posedge clk_in or negedge rst)
    if (~rst)
        flag1 <= 'd0;
    else if(cnt == 'd3 || cnt == 'd6)
        flag1 <= ~flag1; 

always@(negedge clk_in)
    if (~rst)
        flag2 <= 'd0;
    else if(cnt == 'd3  || cnt == 'd6)
        flag2 <= ~flag2;


assign clk_out7 = (flag1 | flag2);
//*************code***********//
endmodule

通用：

`timescale 1ns/1ns

module odo_div_or #(parameter N = 7)
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

parameter cnt_len10 = $clog2(N) -1;
//*************code***********//
reg [cnt_len10:0] cnt;
reg flag1;
reg flag2;
reg clk_out;

always@(posedge clk_in or negedge rst)
    if (~rst)
        cnt <= 'd0;
    else if(cnt == N -1)
        cnt <= 'd0;
    else
        cnt <= cnt + 1'b1;

always@(posedge clk_in or negedge rst)
    if (~rst)
        flag1 <= 'd0;
    else if(cnt == N/2 || cnt == N-1)
        flag1 <= ~flag1; 

always@(negedge clk_in)
    if (~rst)
        flag2 <= 'd0;
    else if(cnt == N/2 || cnt == N-1)
        flag2 <= ~flag2;


assign clk_out7 = (flag1 | flag2);
//*************code***********//
endmodule