题解 | 数据串转并电路

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [2:0] cnt ;
reg [5:0] data_reg;

    always @(posedge clk or negedge rst_n)           
        begin                                        
            if(!rst_n) begin                              
                ready_a <= 1'b0;   
            end                                    
            else begin
                ready_a <= 1'b1;
            end                                                                                                                     
        end

    always @(posedge clk or negedge rst_n)           
        begin                                        
            if(!rst_n) begin                              
                data_reg <= 6'b0;   
            end                                    
            else if(valid_a) begin
                data_reg <= {data_a,data_reg[5:1]};
            end                                                                                  
                                                 
        end

    always @(posedge clk or negedge rst_n)           
        begin                                        
            if(!rst_n) begin                              
                cnt <= 3'b0;   
            end
            else if(cnt == 3'd5) begin
                cnt <= 3'b0;
            end                                   
            else if(valid_a) begin
                cnt <= cnt + 1'b1;
            end                                                                                  
                                                 
        end

    always @(posedge clk or negedge rst_n)           
        begin                                        
            if(!rst_n) begin                              
                valid_b <= 1'b0;   
            end                                    
            else if(cnt == 3'd5) begin
                valid_b <= 1'b1;
            	end                                                                                  
            else begin
                valid_b <= 1'b0;   
            end                                    
        end

    always @(posedge clk or negedge rst_n)           
        begin                                        
            if(!rst_n) begin                              
                data_b <= 6'b0;   
            end
            else if(cnt == 3'd5) begin
                data_b <= {data_a,data_reg[5:1]};
            end   
        end


endmodule