题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);
	reg data_in_r;
	wire data_out_w;
	assign data_out_w = data_in && ~data_in_r;

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)
			data_in_r <= 0;
		else
			data_in_r <= data_in;
	end 
	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)
			data_out <= 0;
		else
			data_out <= data_out_w;
	end 


endmodule
module tb();
	reg clk;
	reg rst_n;
	reg data_in;
	wire data_out;
	initial begin
		clk = 0;
		forever #5 clk = ~clk;
	end 
	initial begin
		rst_n = 0;
		repeat(10)@(posedge clk);
		rst_n = 1;
	end 
	initial begin
		data_in = 0;
		repeat(10)@(posedge clk);
		data_in = 1;
	end 

endmodule