题解 | #ROM的简单实现#
ROM的简单实现
https://www.nowcoder.com/practice/b76fdef7ffa747909b0ea46e0d13738a
`timescale 1ns/1ns module rom( input clk, input rst_n, input [7:0]addr, output wire [3:0]data ); reg [3:0] rom[0:7]; integer i; always @(posedge clk or negedge rst_n) if(!rst_n) for(i = 0; i < 8; i = i + 1) rom[i] = i << 1; assign data = rom[addr]; endmodule
