题解 | #数据累加输出#

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);

reg [1:0] cnt_rcv;
always@(posedge clk, negedge rst_n) begin
	if(!rst_n) cnt_rcv <= 2'd0;
	else if(cnt_rcv == 2'd3 & valid_a & ready_a) cnt_rcv <= 2'd0;
	else if(valid_a & ready_a) cnt_rcv <= cnt_rcv + 2'd1;
end
//拿到第四个数据后，valid_b拉高，并完成累加，等待ready_b,等到后下一时刻拉低
always@(posedge clk, negedge rst_n) begin
	if(!rst_n) valid_b <= 1'b0;
	else if(cnt_rcv == 2'd3 & valid_a & ready_a) valid_b <= 1'b1;
	else if(ready_b) valid_b <= 1'b0;
	else valid_b <= valid_b;
end

//data_out在接收过程中就进行计算，发送完毕后，等待新的接收，否则保持
always@(posedge clk, negedge rst_n) begin
	if(!rst_n) data_out <= 10'd0;
	else if(valid_a & ready_a)
	case(cnt_rcv)
		2'd0:	begin data_out <= data_in; end
		2'd1:	data_out <= data_out + data_in;
		2'd2:	data_out <= data_out + data_in;
		2'd3:	data_out <= data_out + data_in;
	endcase
end

//valid_b拉高即等待发送时，ready_a置低，ready_b到来就同时拉高
assign ready_a = valid_b?(ready_b?1'b1:1'b0):1'b1;

endmodule