题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
reg [3:0]       cnt     ;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt <= 4'd0;
    end
    else if(valid_in)begin
        if(cnt == 4'd15)
            cnt <= 4'b0;
        else 
            cnt <= cnt + 1'b1;
    end
    else 
        cnt <= cnt;
end


always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        valid_out <= 1'b0;
    end
    else if(valid_in)begin
        if(cnt == 'd5 || cnt == 'd10 || cnt == 'd15)
        valid_out <= 1'b1;
        else 
        valid_out <= 1'b0;
    end
	else 
		valid_out <= 1'b0;
end


reg [119:0]     data_out_temp       ;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        data_out_temp <= 'd0;
        data_out <= 'd0;
    end
    else if(valid_in && cnt == 'd5)begin
        data_out_temp <= {data_out_temp[119:16],data_in[15:0]};
        data_out <= {data_out_temp,data_in[23-:8]};
    end
    else if(valid_in && cnt == 'd10)begin
        data_out_temp <= {data_out_temp[119:8],data_in[7:0]};
        data_out <= {data_out_temp[111:0],data_in[23-:16]};
    end
    else if(valid_in && cnt == 'd15)begin
        data_out_temp <= {data_out_temp[119:24],data_in};
        data_out <= {data_out_temp[103:0],data_in};
    end
    else if(valid_in)
        data_out_temp <= {data_out_temp[95:0],data_in};
end
endmodule

在逻辑关系中，if_else结构下注意判断条件