题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0] data
);

reg		[3:0]	addr_init[7:0]		;
// always begin

// end
reg [3:0]data_temp;
always@(*)begin
	if(~rst_n)begin
		data_temp <= 4'b0;
		addr_init[0] = 4'd0			;
		addr_init[1] = 4'd2			;
		addr_init[2] = 4'd4			;
		addr_init[3] = 4'd6			;
		addr_init[4] = 4'd8			;
		addr_init[5] = 4'd10		;
		addr_init[6] = 4'd12		;
		addr_init[7] = 4'd14		;
	end
	else 
		data_temp <= addr_init[addr];
end
assign data = data_temp;

endmodule

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