题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

	reg [2:0]current_state;
	reg [2:0]next_state;
	parameter S0=0;
	parameter S1=1;
	parameter S2=2;
	parameter S3=3;
	parameter S4=4;
	parameter S5=5;

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)
		current_state<=S0;
		else
		current_state<=next_state;
	end

	always@(*)begin
	 case(current_state)

	 S0:begin
		next_state=S1;
	 end

	 S1:begin
		next_state=S2;
	 end

	 S2:begin
		next_state=S3;
	 end

	 S3:begin
		next_state=S4;
	 end

	 S4:begin
		next_state=S5;
	 end

	 S5:begin
		next_state=S0;
	 end
	 default:next_state=S0;
	 endcase
	end

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)
		data<=0;
		else
		case(current_state)
	 S0:begin
		data<=0;
	 end

	 S1:begin
		data<=0;
	 end

	 S2:begin
		data<=1;
	 end

	 S3:begin
		data<=0;
	 end

	 S4:begin
		data<=1;
	 end

	 S5:begin
		data<=1;
	 end
	 default:data<=0;
	 endcase
	end
		




endmodule

摩尔型状态机，输出只与状态有关。需要注意的的三段式中的最后一式，如果是case（current_state)则输出会晚一拍，不过本题好像就是要输出晚一拍