题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter S0 = 4'b0001;
parameter S1 = 4'b0010;
parameter S2 = 4'b0100;
parameter S3 = 4'b1000;

reg [3:0] cs, ns;
always @ (posedge clk or negedge rst) 
begin
    if( ~rst ) begin
        cs <= S0;
    end 
    else begin
        cs <= ns;
    end 
end 

always @ (*) 
begin
    case(cs) 
        S0 : ns = (data == 1'b1) ? S1 : S0;
        S1 : ns = (data == 1'b1) ? S2 : S1;
        S2 : ns = (data == 1'b1) ? S3 : S2;
        S3 : ns = (data == 1'b1) ? S0 : S3;
        default : ns = S0;
    endcase
end 

always @ (posedge clk or negedge rst) 
begin
    if( ~rst ) begin
        flag <= 1'b0;
    end 
    else begin
        if( cs == S3 && data == 1'b1) begin
            flag <= 1'b1;
        end 
        else begin
            flag <= 1'b0;
        end 
    end 
end 

//*************code***********//
endmodule