题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
	reg [2:0]count;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			count<=0;
			ready_a<=0;
		end
		else begin
			ready_a<=1;
			if(valid_a)begin
				if(count==3'd5)begin
					count<=0;
				end
				else begin
					count<=count+1;
				end
			end
		end
	end

	reg [5:0]data_b_reg;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			data_b<=0;
			valid_b<=0;
			data_b_reg<=0;
		end
		else begin
			if(valid_a)begin
				data_b_reg<={data_a,data_b_reg[5:1]};
				if(count==3'd5)begin
					valid_b<=1;
					data_b<={data_a,data_b_reg[5:1]};
				end
				else begin
					valid_b<=0;
					data_b<=data_b;
				end
			end
		end
	end

endmodule

握手协议挺有意思的，可以深挖一下

https://blog.csdn.net/GalaxyerKw/article/details/127513586