题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
	parameter s0=4'b0000,
			  s1=4'b0001,
			  s2=4'b0010,
			  s3=4'b0011,
			  s4=4'b0100,
			  
			  s5=4'b0101,
			  s6=4'b0110,
			  s7=4'b0111,
			  s8=4'b1000,
			  s9=4'b1001;
			 
			  
	reg [2:0] state;
	always@(posedge clk or negedge rst_n)
	if(!rst_n)begin
		state<=s0;
		match<=0;
	end	
	else begin
		case(state)
		s0:begin
			if(data_valid)begin
				if(data==1)begin
					state<=s0;
					match<=0;	
				end
				else begin
					state<=s1;
					match<=0;	
				end
			end
			else begin
				state<=s0;
				match<=0;		
			end
		end

		s1:begin
			if(data_valid)begin
				if(data==1)begin
					state<=s2;
					match<=0;	
				end
				else begin
					state<=s1;
					match<=0;	
				end
			end
			else begin
				state<=s1;
				match<=0;		
			end
		end

		s2:begin
			if(data_valid)begin
				if(data==1)begin
					state<=s3;
					match<=0;	
				end
				else begin
					state<=s1;
					match<=0;	
				end
			end
			else begin
				state<=s2;
				match<=0;		
			end
		end

		s3:begin
			if(data_valid)begin
				if(data==1)begin
					state<=s0;
					match<=0;	
				end
				else begin
					state<=s4;
					match<=1;	
				end
			end
			else begin
				state<=s3;
				match<=0;		
			end
		end

		s4:begin
			if(data_valid)begin
				if(data==1)begin
					state<=s0;
					match<=0;	
				end
				else begin
					state<=s1;
					match<=0;	
				end
			end
			else begin
				state<=s4;
				match<=0;		
			end
		end

		
		default:;
		endcase
	end	  

  
endmodule