题解 | #时钟分频（偶数）#d触发器版

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//

wire clk2,clk4,clk8;

dff u1(
    .clk_d(clk_in),
    .rst_n(rst),
    .d(~clk2),

    .q(clk2)
);
dff u2(
    .clk_d(clk2),
    .rst_n(rst),
    .d(~clk4),

    .q(clk4)
);
dff u3(
    .clk_d(clk4),
    .rst_n(rst),
    .d(~clk8),

    .q(clk8)
);

assign clk_out2=clk2;
assign clk_out4=clk4;
assign clk_out8=clk8;
//*************code***********//
endmodule

module dff(
    input clk_d,
    input rst_n,
    input d,

    output reg q
);

always@(posedge clk_d or negedge rst_n)begin
    if(~rst_n)
        q<=0;
    else
        q<=d;
end
endmodule