题解 | #同步FIFO#

`timescale 1ns/1ns
/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  //深度对2取对数，得到地址的位宽。
	,input [WIDTH-1:0] wdata      	//数据写入
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  //深度对2取对数，得到地址的位宽。
	,output reg [WIDTH-1:0] rdata 		//数据输出
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/**********************************SFIFO************************************/
module sfifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					clk		, 
	input 					rst_n	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output reg				wfull	,
	output reg				rempty	,
	output wire [WIDTH-1:0]	rdata
);

reg	[$clog2(DEPTH):0] waddr;// 多一位位宽
reg	[$clog2(DEPTH):0] raddr;
wire wenc;
wire renc;

assign wenc = winc && !wfull;
assign renc = rinc && !rempty;

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		waddr <= 0;
		raddr <= 0;
	end
	else begin
		if(wenc) begin
			waddr <= waddr + 1;
		end
		if(renc) begin
			raddr <= raddr + 1;
		end
	end
end

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		wfull <= 0;
		rempty <= 0;
	end
	else begin 
		if (raddr == {~waddr[$clog2(DEPTH)], waddr[$clog2(DEPTH)-1:0]}) // 低位一样，高位取反
			wfull <= 1;
		else
			wfull <= 0;
		if (raddr == waddr)
			rempty <= 1;
		else
			rempty <= 0;
	end
end

dual_port_RAM dual_port_RAM_u (
	.wclk	(clk),
	.wenc	(wenc),
	.waddr	(waddr),
	.wdata	(wdata),
	.rclk	(clk),
	.renc	(renc),
	.raddr	(raddr),
	.rdata	(rdata)
);

endmodule