题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

reg [1:0] cur_state;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cur_state <= 0;
    end
    else begin
        case (cur_state)
            0:  cur_state <= C ? 1 : 0;
            1:  cur_state <= C ? 1 : 3;
            2:  cur_state <= C ? 2 : 0;
            3:  cur_state <= C ? 2 : 3;
        endcase
    end 
end

assign Y = (cur_state == 3) | (cur_state == 2 & C);

endmodule