题解 | #优先编码器Ⅰ#

`timescale 1ns/1ns

module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
wire [8:0] check;
reg [2:0]  Y_r;
reg GS_r,EO_r;
assign GS = GS_r;
assign EO = EO_r;

assign Y = Y_r;
assign check = {EI,I};
always@(*)
begin
  casex(check)
  9'b0_xxxx_xxxx: begin Y_r=3'b000; GS_r=1'b0; EO_r=1'b0; end 
  9'b1_0000_0000: begin Y_r=3'b000; GS_r=1'b0; EO_r=1'b1; end 
  9'b1_1xxx_xxxx: begin Y_r=3'b111; GS_r=1'b1; EO_r=1'b0; end 
  9'b1_01xx_xxxx: begin Y_r=3'b110; GS_r=1'b1; EO_r=1'b0; end 
  9'b1_001x_xxxx: begin Y_r=3'b101; GS_r=1'b1; EO_r=1'b0; end 
  9'b1_0001_xxxx: begin Y_r=3'b100; GS_r=1'b1; EO_r=1'b0; end
  9'b1_0000_1xxx: begin Y_r=3'b011; GS_r=1'b1; EO_r=1'b0; end
  9'b1_0000_01xx: begin Y_r=3'b010; GS_r=1'b1; EO_r=1'b0; end
  9'b1_0000_001x: begin Y_r=3'b001; GS_r=1'b1; EO_r=1'b0; end
  9'b1_0000_0001: begin Y_r=3'b000; GS_r=1'b1; EO_r=1'b0; end
  default:begin Y_r=3'b000; GS_r=1'b0; EO_r=1'b0; end 
  endcase



end




endmodule