题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg [2:0]state_next;
reg [2:0]state;
reg [7:0]d_r;

always@(posedge clk or negedge rst)
begin
if(~rst)begin
state <= 3'h0;
end
else begin
state <= state_next; end
end

always@(*)
begin
    case (state)
 3'h0:begin d_r = d; state_next =  3'h1; end
 3'h1: state_next =  3'h2;
 3'h2: state_next =  3'h3;
 3'h3: state_next =  3'h4;
 3'h4: begin d_r = d; state_next =  3'h1; end
 default: begin d_r = 8'h0; state_next =  3'h1; end
    endcase

end
always@(posedge clk or negedge rst)
begin
if(~rst)
  begin
  out <= 11'h0;
  input_grant <= 1'b0;
  end
else begin
case(state_next)
 //3'h0: begin out <= 11'h0;  input_grant <= 1'b0;end
 3'h1: begin out <= {3'h0,d_r};  input_grant <= 1'b1;end
 3'h2: begin out <= d_r*2'd3;  input_grant <= 1'b0;end
 3'h3: begin out <= d_r*3'd7;  input_grant <= 1'b0;end
 3'h4: begin out <= d_r<<3;  input_grant <= 1'b0;end
 default:  begin out <= 11'h0;  input_grant <= 1'b0;end
endcase
end
end
//*************code***********//
endmodule