题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output  q  
);
//*************code***********//
wire mid;
t_gite u1(
.data(data),
.rst(rst),
.clk(clk),
.q(mid)
);

t_gite u2(
.data(mid),
.rst(rst),
.clk(clk),
.q(q)
);




//*************code***********//
endmodule


module t_gite(data,rst,clk,q);
input wire data ,rst ,clk;
output reg q;

always@(posedge clk or negedge rst)
begin
if(~rst)
q <= 1'b0;
else if(data)
q <= ~q;
else
q <= q;
end
endmodule