题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//

//智障题目，非要使用状态机
reg [1:0] state;
always@(posedge clk or negedge rst)
  if(!rst)
    state <= 2'd0;
  else if(state==2'd3 )
    state <= 2'd0;
  else 
    state <= state + 2'd1;

always@(posedge clk or negedge rst)
  if(!rst)
    clk_out <= 1'd0;
  else case(state)
    2'd0:clk_out <= 1'b1;
    default:clk_out <= 1'b0;
  endcase



//*************code***********//
endmodule