题解 | #加减计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);

	reg [3:0]num;
	always @(posedge clk or negedge rst_n)
		if (!rst_n)
			begin 
				zero <= 1'd0;
			end
		else if (num == 4'd0)
			begin
				zero <= 1'b1;
			end
		else 
			begin	
				zero <= 1'b0;
			end
		
	always @(posedge clk or negedge rst_n)
		if (!rst_n)
			begin 
				num <= 4'b0;
			end
		else if(mode)
			begin
				if(num == 9)
					num <= 0;
				else
					num <= num + 1'd1;
			end
		else if(!mode)
			begin
				if(num == 0)
					num <= 9;
				else
					num <= num - 1'd1;
			end
		else num <= num;
		
	always @(posedge clk or negedge rst_n)
		if (!rst_n)
			begin 
				number <= 4'd0;
			end
		else 
			begin	
				number <= num;
			end
endmodule

要同时考虑一下加减的置位。