题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//

reg                 [2:0]               cnt;
always@(posedge clk_in or negedge rst)
    if(!rst)
        cnt <= 3'd0;
    else if(cnt >= 3'd4)
        cnt <= 3'd0;
    else
        cnt <= cnt + 1'b1;
assign clk_out5 = ((cnt==3'd1)||(cnt == 3'd2))? 1'b1:1'b0;
//*************code***********//
endmodule