题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
reg 				[3:0] 				sq,sq_r;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		sq_r <= 4'd0;
	else if(data_valid)
		sq_r <= {data,sq_r[3:1]};
	else
		sq_r <= sq_r;
	
always@(posedge clk or negedge rst_n)
	if(!rst_n) begin
		match <= 1'b0;
		sq <= sq;
	end
	else if(data_valid)begin
		// sq_r <= {data,sq[3:1]};   
		if({data,sq_r[3:1]} == 4'b0110) begin
			sq <= {data,sq_r[3:1]};
			match <= 1'b1;
		end
		else begin
			match <= 1'b0;
			sq <= sq ;
		end
	end
	else begin
		match <= 1'b0;
		sq <= sq;
	end
  
endmodule