题解 | #全加器#

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);

wire s_0,c_0;
wire s_1,c_1;

add_half u_0(A,B,s_0,c_0);
add_half u_1(s_0,Ci,s_1,c_1);

assign S = s_1;
assign Co = c_0 | c_1;

endmodule

// 原理如下
// A,B -> A^B , AB
// (A^B),Ci -> A^B^C , (A^B)&Ci

// S = A^B^C
// Co = AB | (A^B)&Ci