题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff(
    input T,
    input rst,
    input clk,
    output reg Q
);
    
    always@(posedge clk or negedge rst)begin
        if(!rst)
            Q <=1'b0;
        else if(T)
            Q <= ~Q;
        else
            Q <= Q;
    end 
    
endmodule

module Tff_2 (
input wire data, clk, rst,
output wire q  
);
//*************code***********//
wire q0;

Tff Tff1(
    .T(data),
    .rst(rst),
    .clk(clk),
    .Q(q0)
);

Tff Tff2(
    .T(q0),
    .rst(rst),
    .clk(clk),
    .Q(q)
);
//*************code***********//
endmodule

补充大佬的笔记：

注意：如果报错

cannot be driven by primitives or continuous assignment

Output port expression must support continuous assignment.

那是因为reg不应连接到模块输出，改成wire就好