题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
reg [2:0] cnt;
always @(posedge clk_in or negedge rst) begin
    if(!rst) begin
        cnt <= 0;
    end
    else begin
        cnt <= (cnt == 4)?0 : (cnt + 1'b1);
    end
end

reg clk_out5_reg;
always @(posedge clk_in or negedge rst) begin
    if(!rst) begin
        clk_out5_reg <= 0;
    end
    else if (cnt == 0 || cnt == (5-1)/2) begin
        clk_out5_reg <= ~clk_out5_reg;
    end
    else begin
        clk_out5_reg <= clk_out5_reg;
    end
end

assign clk_out5 = clk_out5_reg;



//*************code***********//
endmodule