题解 | #多位信号xnor#

`timescale 1ns/1ns

module top_module(
    input a, b, c, d, e,
	output [24:0] out
);
wire [24:0] out1,out2;
reg [24:0] out_flag;
assign out1={{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}};
assign out2={5{a,b,c,d,e}};
integer i;
always@(out1,out2)
begin
    for(i=0;i<=24;i=i+1)
    begin
    out_flag[i]=~(out1[i]^out2[i]);
    end
end
assign out=out_flag;
endmodule