题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg [2:0] cnt;
always @(posedge clk_in or negedge rst or negedge clk_in) begin
    if(!rst) begin
        cnt <= 0;
    end
    else if (cnt >= 6) begin
        cnt <= 0;
    end
    else begin
        cnt <= cnt + 1'b1;
    end
end

reg clk_out7_reg;
always @(posedge clk_in or negedge rst or negedge clk_in) begin
    if(!rst) begin
        clk_out7_reg <= 0;
    end
    else if (cnt >= 6) begin
        clk_out7_reg <= ~clk_out7_reg;
    end
    else begin
        clk_out7_reg <= clk_out7_reg;
    end
end
assign clk_out7 = clk_out7_reg;
//*************code***********//
endmodule