题解 | #8线-3线优先编码器实现16线-4线优先编码器#

`timescale 1ns/1ns
module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);

assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];

assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
         
endmodule
module encoder_164(
   input      [15:0]      A   ,
   input                  EI  ,
   
   output wire [3:0]      L   ,
   output wire            GS  ,
   output wire            EO    
);
wire GSH,GSL,EOH;
wire [2:0]  Y_H,Y_L;
encoder_83 U_H(
    .I  (A[15:8]),
    .EI (EI),
    .Y  (Y_H),
    .GS (GSH),
    .EO (EOH)
);
encoder_83 U_L(
    .I  (A[7:0]),
    .EI (EOH),
    .Y  (Y_L),
    .GS (GSL),
    .EO (EO)
);

assign L = EI ? (EOH ? {1'b0,Y_L} :{1'b1,Y_H}) : 0;
assign GS= GSH | GSL;

endmodule