题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);

reg [1:0] Cur_state ;
reg [1:0] Nxt_state ;
reg y;
always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        Cur_state <= 0;
    end
    else 
        Cur_state <= Nxt_state ;
end

always@(*) begin
    case(Cur_state)
        2'b00:if(A==0)
                Nxt_state = 2'b01 ;
              else
                Nxt_state = 2'b11 ;
        
        2'b01:if(A==0)
                Nxt_state = 2'b10 ;
              else
                Nxt_state = 2'b00 ;
        
        2'b10:if(A==0)
                Nxt_state = 2'b11 ;
              else
                Nxt_state = 2'b01 ;
        
        2'b11:if(A==0)
                Nxt_state = 2'b00 ;
              else
                Nxt_state = 2'b10 ;
    endcase

end

always@(*) begin 
    if(!rst_n) 
        y = 0;
    else if(Cur_state == 2'b11)
        y = 1;
    else    
        y = 0 ;
end

assign Y = y ;

endmodule