题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	// cnt
	reg [2:0] cnt;
	always @(posedge clk, negedge rst_n) begin
		if(!rst_n) begin
			cnt <= 0;
		end
		else begin
			cnt <= (cnt == 5)? 0 : cnt + 1;
		end
	end

	// data shift
	reg [5:0] data_r;
	always @(posedge clk, negedge rst_n) begin
		if(!rst_n) begin
			data_r <= 0;
		end
		else begin
			data_r <= {data_r[4:0], data};
		end
	end

	// match
	always @(posedge clk, negedge rst_n) begin
		if(!rst_n) begin
			match <= 0;
			not_match <= 0;
		end
		else if(cnt == 5) begin
			match     <= ({data_r[4:0], data} == 6'b011100);
			not_match <= !match;//({data_r[4:0], data} != 6'b011100);
		end
		else begin
			match <= 0;
			not_match <= 0;
		end
	end

endmodule

第三段的 not_match <= !match 结果错误，这是为什么呢？