题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

reg [2:0]c_state;
reg [2:0]n_state;
reg [2:0]cnt;
parameter cnt_max = 3'd6;

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	    c_state <= 3'd0;
	else
	    c_state <= n_state;
end

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	    cnt <= 3'd0;
	else if(cnt < cnt_max - 1)
	    cnt <= cnt + 1;
	else
	    cnt <= 3'd0;
end




always@(*)
begin
	if(!rst_n)
	    n_state = 3'd0;
	else begin
        case(c_state)
		    3'd0:begin
				if(!data && cnt == 3'd0)
				    n_state = 3'd1;
				else
				    n_state = 3'd0;
			end
			3'd1:begin
				if(data && cnt == 3'd1)
				    n_state = 3'd2;
				else
				    n_state = 3'd0;
			end
			3'd2:begin
				if(data && cnt == 3'd2)
				    n_state = 3'd3;
				else
				    n_state = 3'd0;
			end
			3'd3:begin
				if(data && cnt == 3'd3)
				    n_state = 3'd4;
				else
				    n_state = 3'd0;
			end
			3'd4:begin
				if(!data && cnt == 3'd4)
				    n_state = 3'd5;
				else
				    n_state = 3'd0;
			end
			3'd5:begin
				    n_state = 3'd0;
			end
			default:n_state = 3'd0;
		endcase
	end  
end

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)begin
	    match <= 0;
		not_match <= 0;
	end
	else if(c_state == 3'd5 && !data)
	    match <= 1;
	else if(cnt == 3'd5 && c_state == 0)
	    not_match <= 1;
	else begin
		match <= 0;
		not_match <= 0;
	end
end






endmodule